I am an assistant professor (tenured) in the Computer Architecture for Embedded Systems (CAES) group at the University of Twente (NL). Previously, I was a Postdoc in Design Automation for Embedded Systems Group from 2019 to 2021. I did my PhD in Computer Science between November 2014 and May 2019 in TU Dortmund, Germany. Before my PhD, I received my bachelor and master degrees in “Interdisciplinary Program of Humanities and Social Sciences” (2011) and Computer Science (2013) respectively, from National Tsing-Hua University in Taiwan.
My research interests span a wide spectrum, ranging from intricate algorithms to detailed compilation processes. Particularly, I focus on hardware-software co-design automation and bridge the gap between theory and practice in real-time system software. In addition to my academic pursuits, I am committed to mentorship, engaging in programs such as Google and ESA Space Summer of Code. Furthermore, I am passionate about contributing to open-source development, with a particular emphasis on RTEMS. This multifaceted dedication reflects my enthusiasm for both theoretical exploration and hands-on implementation in the ever-evolving landscape of technology.
Download my CV (updated on Sep 2023)
PhD in Computer Science (Dr.-Ing., with the highest distinction "summa cum laude"), 2019
TU Dortmund University, Germany
MSc in Computer Science, 2013
National Tsing-Hua University in Taiwan
BA in Computer Science (Minor) / Humanities and Social Sciences (Major), 2011
National Tsing Hua University in Taiwan
My journey in Europe
Safety-critical systems are often subjected to transient faults. Since these transient faults may lead to soft errors that cause catastrophic consequences, error-handling must be addressed by design. Full-protection against faults is too costly in terms of resource usage. A common approach to relax the resource demands and limit the impact of errors is to consider (m, k)-constraints, which requires that at least $m$ jobs out of any k consecutive jobs are error-free. To assure (m, k)-compliance, static patterns are widely used to select the job execution modes, i.e., either in an error-free mode at the cost of increased worst-case execution time or in an error-prone mode with the advantage of less execution time.
Although static patterns have been shown to be effective in energy-aware designs, resource over-provision is inevitable due to the relatively low rate of error probability. In this work, we propose two dynamic (and adaptive) approaches that allow the scheduler to dynamically select execution modes based on the error-history of the past jobs and the actual error probability. We firstly propose a Markov Chain based solution if the error-probability is known and static and secondly a reinforcement learning-based approach that can handle unknown error probabilities. Experimental evaluations show that our approaches outperform the state-of-the-art in most of the evaluated cases in terms of average utilization for each task and the overall utilization for multitask systems.
In soft real-time systems, tasks may occasionally miss their deadlines. This possibility has triggered research on probabilistic timing analysis for the execution time of a single program and probabilistic response time analysis of concurrently executed tasks. Under fixed-priority preemptive uniprocessor scheduling, it was shown that the classical critical instant theorem (for deriving the worst-case schedulability or response time) by Liu and Layland (in JACM 1973) can be applied to analyze the worst-case deadline failure probability (WCDFP) and the worst-case response time exceedance probability (WCRTEP). In this work, we present a counterexample for this result, showing that the WCDFP and WCRTEP derived by the classical critical instant theorem is unsound. We further provide two sound methods: one is to account for one additional carry-in job of a higher-priority task and another is to sample and inflate the execution time of certain jobs without adding one additional carry-in job. We show that these two methods do not dominate each other and, in the evaluation, apply them to two well-known approaches based on direct convolution and Chernoff bounds.
Modern low power distributed systems tend to integrate machine learning algorithms. In resource-constrained setups, the execution of the models has to be optimized for performance and energy consumption. Racetrack memory (RTM) promises to achieve these goals by offering unprecedented integration density, smaller access latency, and reduced energy consumption. However, to access data in RTM, it needs to be shifted to the access port first. We investigate decision trees and develop placement strategies to reduce the total number of shifts in RTM.
For timing-sensitive edge applications, the demand for efficient lightweight machine learning solutions has increased recently. Tree ensembles are among the state-of-the-art in many machine learning applications. While single decision trees are comparably small, an ensemble of trees can have a significant memory footprint leading to cache locality issues, which are crucial to performance in terms of execution time. In this work, we analyze memory-locality issues of the two most common realizations of decision trees, i.e. native and if-else trees. We highlight, that both realizations demand a more careful memory layout to improve caching behavior and maximize performance.